Two-dimensional transistors with reconfigurable polarities for secure circuits

Two-dimensional transistors with reconfigurable polarities for secure circuits

Our journey with black phosphorus (BP) started in a project working on building tunnel field-effect transistors (TFETs) using 2D materials. One of the key challenges was to introduce doping in BP, since a TFET requires a p-i-n doping profile. However, doping in 2D materials has always been an issue, as traditional ways of introducing substitutional dopant atoms – ion implantation or diffusion – remains challenging for atomically thin 2D materials. We ended up with a solution using multiple gates to introduce the desired doping profile in different segments of the BP channel by electrostatic doping and demonstrated a BP TFET. We also found that if we change the doping profile of the BP device by changing the combination of gate biases, we can reconfigure the device into a TFET or a MOSFET, and into a p-type device or an n-type device. The work was later published in ACS Nano.

Fig. 1. Schematic and a false-colored SEM image of a reconfigurable BP TFET, where our reconfigurability idea started. Reprinted with permission from ACS Nano. Copyright 2019 American Chemical Society.

In short, the reconfigurability was kind of a by-product in our TFET project when introducing electrostatic doping. After the TFET project ended, we started to think of some applications that can make use of the reconfigurability. This was when we became aware of the idea of polymorphic gates, proposed by Prof. Sharon Hu and her collaborators, which takes advantage of the reconfigurability of transistors to build secure circuits. Before, there have been some prototype demonstrations using other material systems, such as silicon nanowires, yet they suffer from issues such as low on-currents, large supply voltage, etc. We felt we could make a difference by using BP as channel material, since the small bandgap of BP implies a small barrier height for both electrons and holes in a Schottky-barrier FET, which in turn translates into higher on-currents. We later on also realized that a small bandgap is also necessary for scaling down the threshold voltages of a reconfigurable transistor, meaning that both axes of the IdVg characteristics benefit from the small bandgap!

After a few rounds and iterations of improving device structures (which actually took more than a year), we finally reached optimized device performance – near ideal SS, good on-off ratios, low-voltage operation, good symmetry between p-type and n-type characteristics – everything looked great on the single device level. The next step was to wire up these transistors to form a working circuit. Since we used scotch-tape exfoliation to transfer the BP flakes onto the substrate, the transistors were scattered around at different locations on a 1 cm × 1 cm silicon chiplet. As a result, we had to make wires that are millimeters long and tens of micrometers wide to connect these transistors – so wide that they can be seen with the naked eye. Of course, this is sort of an ad hoc solution for the prototype circuit and a tighter integration should be explored, but it does give us a feel of the ‘good old days’ when the monolithic silicon IC was first invented, when everything was brand new and in a rough shape, and we hope that one day our design could also grow into something big. 

Fig. 2. (a) Photo of our secure chip. (Purdue University photo/John Underwood) (b) Photo of first monolithic silicon IC chip.

For more information, please check out our article “Two-dimensional transistors with reconfigurable polarities for secure circ­uits”.