Neuromorphic engineers seek to emulate the principles of computation observed in the human brain with artificial hardware. While the details of brain function have been an inexhaustible source of debate, one characteristic of the brain is settled – it is complex. This complexity is derived from both the dynamics of the individual synaptic and neuronal components and the massive scale of connectivity – 100 billion neurons connected through 100 trillion synapses. An intriguing exercise is to ask, “What artificial system would be best suited for achieving (and even superseding) such a scale?”
To many, silicon microelectronics may appear as the obvious solution. Certainly, neuromorphic CMOS has and will continue to push the field forward. However, as we target ever larger networks, digital event routing systems will struggle to maintain low-latency communication between neurons. This leads to a speed vs. connectivity tradeoff in communication-limited networks. Our group at NIST has been pursuing a different approach that uses optical pulses to represent spiking activity and enables direct fan-out from one neuron to potentially thousands of downstream synapses. This fully dedicated approach – a light source for every neuron, a detector for every synapse, and a dedicated waveguide between them – would allow light-speed communication between electronic neurons independent of network scale. We imagine this hardware finding utility in datacenter-scale applications – from high-performance computing to massive artificial intelligence systems that leverage the temporal dynamics, learning algorithms, and connectivity that make biological neural networks so efficient and effective.
Constructing a system with so many integrated sources, detectors, and active electronics for computation at each unit is a major challenge, and several groups are pursuing different physical platforms to achieve similar visions. Our group’s view is distinct, however, in that we think superconducting electronics is uniquely suited for this application. The advantages of superconducting electronics for optoelectronic neuromorphic computing include: (1) superconducting-nanowire single-photon detectors (SNSPDs) are simple to fabricate and enable optical signaling at the single-photon limit, (2) Josephson junctions (JJs) provide efficient analog implementations of many synaptic and neuronal functions, and (3) cryogenic temperatures make the goal of efficient integrated light sources more attainable. In this work, we present synaptic circuits constructed with SNSPDs and JJs demonstrating points (1) and (2).
Each circuit consists of a current-biased SNSPD wired to a JJ (Fig. 1a). Upon photon detection, current is diverted away from the SNSPD and drives the JJ above its critical current, Ic. After propagating through a Josephson transmission line, fluxons produced by the JJ are stored as circulating current (Isi) in a superconducting loop. This allows photon detection events to be integrated over time (Fig. 1c) and stored in the integration loop. The integrated current is then converted to a voltage (Vsq) using an inductively coupled SQUID on-chip. By adding resistors to the integration loops, the synapses become leaky integrators analogous to their biological counterparts. One of the exciting results of this study was how well the same circuit design worked with many different values of leak rate (set by the ratio of loop inductance to resistance). We demonstrate synaptic time constants spanning about 250 ns to 5 ms and have since also fabricated entirely non-leaky synapses. Different time constants will be optimal for different applications, so this speaks well to the wide applicability of this hardware in the future.
We also show that the synaptic weight can be easily tuned with a bias current (Isy) to the first JJ (Fig. 1d). Increasing this bias causes more fluxons to be added to the integrating loop each time the SNSPD detects a photon. We show the ability to smoothly tune the weight from 0 to more than 500 nA/photon. While near-term demonstrations may be feasible with this weighting mechanism, large-scale systems will clearly require some variety of synaptic memory. We have proposed the use of programmable superconducting loops and plan to explore this path in the future.
All experiments were conducted at a temperature of around 1K. A fiber positioned above the sample was used to flood illuminate the chip using a pulsed laser. We confirmed single photon operation of our circuits with a linearity measurement under low illumination conditions. This, combined with the lack of number resolution in SNSPDs and the short duration of our laser pulses (~480 ps), make us confident that our synapses will respond similarly in the few-photon regime with the addition of integrated photonics in future experiments. The addition of these photonic components—integrated light-sources and waveguides—will be the next proof-of-principle demonstration of the feasibility of the neuromorphic platform.
The 14-layer fabrication process developed for this work is, to our knowledge, the first-ever monolithic integration of SNSPDs and JJs. While motivated by neuromorphic computing, we hope this achievement will have an impact across a range of fields. For instance, digital SFQ (single flux quantum) circuits have been explored for readout of large-scale SNSPD arrays for many years, and we are excited to see if this result could aid in that endeavor. As we show in the paper, the longest time constant synapse is already acting similarly to a photon-counting pixel. A future goal is to demonstrate single-photon to single-fluxon transduction in non-leaky loops to make true photon counting pixels that could be valuable for a variety of imaging and quantum information applications. We are eager to hear from readers if they have any other applications in mind that might benefit from the monolithic integration of these two foundational superconducting devices.
Link to paper: https://www.nature.com/articles/s41928-022-00840-9
Please sign in or register for FREE
If you are a registered user on Nature Portfolio Engineering Community, please sign in