There is a general interest in combining electronic and photonic function on the same chip. This can be either to drive new functionality such as integrated sensors or to use photons as the signal carrier instead of electrons to either speed up or improve the power consumption via on-chip optical communication.
Silicon is a fantastic material, it is cheap, abundant and has been the foundation of the revolution in the information technology. Also, in terms of optical properties, it is ideal for waveguiding because of low optical loss for wavelengths above 1.1 mm. Its indirect bandgap, however, makes it unsuitable for light emission, and less efficient as a detector in particular in the telecom bands.
Compounds of III-V materials on the other hand present not only a direct bandgap but also the possibility for tuning the wavelength by composition tuning, and for improving active device performance by the use of heterojunctions. This makes it possible to fabricate lasers and LED, and for photodetectors III-Vs generally provide lower dark currents and higher sensitivity for longer wavelengths compared to SiGe based devices. It has therefore been a long-sought goal to combine silicon and III-Vs on the same silicon platform.
There are a number of approaches to grow III-V on silicon. Growing a planar sheet of III-V on top of silicon typically creates a poor-quality material because the two materials are not lattice matched and have different thermal expansion coefficients and polarities. The most common method for advanced photonic applications is to bond a III-V wafer or individual III-V components on top of the Si wafer. Alternatively, nanowire (NW) growth allows for the growth of high-quality III-V NWs directly on silicon. In this way it is possible to achieve high-quality material, but the aspect ratio of the NWs along with the vertical orientation makes the large-scale integration of more advanced devices challenging.
In this work we present a novel approach for monolithic integration of III-V on Si for photonics. The Template-Assisted Selective-Epitaxy technology developed at IBM, enables the growth of complex nanostructures along the surface of an SOI wafer. In the embodiment used in this work we grow an InGaAs NW from a Si seed on an SOI wafer. The growth extends along the surface of the wafer and includes in-situ growth of a p-i-n doping profile in-plane. The high degree of control achievable in this method allows us to place contacts accurately on the scaled devices.
The fabricated devices show diode-like characteristics with light emission under forward bias and light detection when operated under reverse bias in the telecommunication bands.
TCAD simulations are used to support the experimental work, and we observe that the geometrical features, such as the only 60 nm thin InGaAs film and the contact design, play an important role in optimizing the spectral response, resulting in absorption peaks in the important wavelength regions around 1300 nm and 1600 nm.
To demonstrate the full potential of the monolithic nanowire detectors, we conduct high-speed photo detection measurements relevant for optical communication. The devices show a 3 dB data reception at 32 Gbps.
This work represents a crucial step towards locally integrated and scaled III-V photodetector in silicon photonics integrated circuits.