Our work on nanoscale vacuum channel transistors (NVCTs) didn’t quite evolve or happen in vacuum, no pun intended. In my ten years at NASA Ames Research Center in Silicon Valley (and little more than twice as long for my senior colleague Meyya Meyyappan), we have always realized that NASA doesn’t get to use the latest and greatest in electronics in space missions. This is because you simply can’t fly commercial-off-the-shelf electronics to space due to their vulnerability to radiations. Single event latch-up in CMOS, total ionizing dose effects manifesting as gradual on-current reduction and off-state leakage increase, displacement damage and others are some of the problems facing electronics traveling through serious radiation environment. What are the counter measures? How NASA has been flying electronics all these years? One can limit the flight path to minimize the radiation exposure but that leads to delays and constrains the exploration area. Chip designs with radiation awareness have been used before but this approach is expensive and limits the options since not everything needed may be available in space-grade pool of electronics. Another popular option is to wrap the electronics in radiation shielding based on a metal chassis; an ultimate example of this “mummification of electronics" is the Juno radiation vault in the Juno spacecraft to Jupiter. It had a vault with 1 cm thick titanium metal weighing 200 Kg to protect the electronics from getting fried by the intense radiation belt around Jupiter. This armor adds incredible weight penalty to an otherwise tiny system of circuits and architectures, impacting launch costs.
Wouldn’t it be nice if we don’t have to worry too much about radiation? For all its faults, we know the old vacuum electronics was immune to radiation. So I suggested to my NASA colleagues: why not marry the best of vacuum electronics and modern integrated circuit manufacturing? We know the similarity between the vacuum tube and transistor, and so it is worth making the transistor in conventional way with emptiness as channel instead of silicon, thus making them as small and cheap as MOSFETs. This was the genesis of our NVCT research at NASA Ames. Our early work with a vacuum channel length of only 50 nm and a gate wrapping around the channel gave very good performance operating at only 2V and providing about 10 µA; the fabrication was done on 200 mm wafers from day one since it was all silicon and routine fabrication (see Nano Letters, 17, 2146-2151, 2017). We even measured cut-off frequency close to 0.5 THz for un-optimized early devices. But there was something bothering my colleague Meyyappan, and he wasn’t satisfied with the drive current, which was quite a bit smaller than a MOSFET of the same size. That was because the same size source pad with the same doping level was shaped into a single tip with a 10 nm radius of curvature in the NVCT, which limited the current. When I told him that, his question was: who says we can only have one tip when it is really a waste of the source pad real estate? In this Nature Electronics paper, we demonstrate a vertical NVCT in both SiC and silicon systems with multiple emitters on the source pad that shows current scaling with the number of emitters, thus giving design choice to achieve the desired current and power levels. We also show reliability of the NVCT against gamma and neutron radiations.
What is next? Making circuits, which is currently under way. Is the utility of NVCT limited only to NASA? Not really; with today’s device sizes, radiation is a concern even in terrestrial applications. A 6 nm FINFET size is comparable to the displacement damage cluster due to terrestrial cosmic radiation, which is constantly tampering with our electronics. The terrestrial neutron flux at New York sea level is about 20/cm2/hr. with 1-100 MeV energy, which is energetic enough to cause displacement and accumulate over time. There are many other examples of radiation impact on highly scaled ultrasmall terrestrial electronic devices, suggesting the need to pay attention to this aspect regardless of what novel materials and device designs we embrace. Then, there is the speed advantage; electrons are blazingly fast in vacuum compared to semiconductors including all the emerging 2D materials. This, combined with amenability to conventional fabrication techniques, makes NVCT a competitive avenue in the post-Moore’s law era that is seeking alternatives. Is the need for vacuum a limitation? No, it is not onerous since a 50-nm channel is smaller than the mean free path at atmospheric pressure and the channel is already under quasi-vacuum. Maintaining a vacuum level of 10-100 mTorr may be adequate in order to increase the reliability and robustness, which is a far cry from the 10-10 Torr working vacuum level of the early devices.
This is the story of going back to the future. The technology has potential, given its history, simplicity and absence of anything exotic. What we need is a larger community involvement. Our group doesn’t expect to and can’t solve all the problems. I am reminded of the popular phrase heard around in recent years when requiring community efforts: it takes a village to (fill in the blanks). Fortunately, we see researchers showing interest in this area. There is a big effort on empty state electronics at MIT funded by an Air Force MURI (Multi-University Research Initiative), besides several individual researchers in the US and China. Finally, I am reminded of an anecdote I heard about a congressional delegation visiting NASA Marshall Space Flight Center in the early days of the space program. When asked how the rocket goes up, one of the engineers tried to explain in excruciating details but was interrupted by an impatient colleague saying that it is simple, the funding makes the rocket go up. In that spirit, let us hope more groups across the world get funding to address the possibilities of using nanoscale vacuum devices for electronic circuits, THz electronics, satellite communication, and many others.
If you want to see more, please find our paper recently published in Nature Electronics, Nanoscale vacuum channel transistors fabricated on silicon carbide wafers