Realization of a logic gate in a single 2D channel

In this work, we fabricated an "all-2D" single channel logic device utilizing highly efficient local electrostatic gating.
Realization of a logic gate in a single 2D channel

For last few decades, there has been a lot of effort devoted to the reduction of channel length in electronic devices. Now, it has been demonstrated that channel length reaches down to a few nanometers by using carbon nanotubes and 2D materials. However, to obtain a higher density of integration, footprint of the device, including channel, gate, and contact, should be reduced. Although the channel length was scaled down to sub-10 nm, the length of source and drain contacts is still as large as tens of nanometers due to area-dependent contact resistance. Therefore, many researchers have tried to reduce contact resistance using various methods. However, we focused on the other way to reduce total size of a logic device. 

“Another way is to realize multi-logics in a single channel!”

In this study, we utilize two-dimensional (2D) materials for fabricating high performance field-effect transistors (FETs) and single channel logic devices. Also, the “all-2D” device platform is realized from van der Waals heterostructures which are made of different 2D layers stacked in the designed sequence. To this end, we utilized one of the most important properties of 2D channels, high gate tunability due to their atomic thinness. Hence, it is possible that a 2D channel with local gates is sharply separated to quasi-single devices.

We first fabricated an “all-2D” device platform by using ReS2 (or ReSe2), graphene and hBN as channel, electrode and dielectric, respectively. ReS2 and ReSe2 show unique properties compared to other transition metal dichalcogenides (TMDCs) due to their lack of interlayer coupling. Graphene contacts show reasonably small contact resistance, similar to previous reports in n-type MoS2. Our electrical measurements show that a combination of 2D materials for “all-2D” devices is promising for high device performance in terms of carrier mobility (35 cm2/V·s) and on-off ratio (= 106).

Then, we expected that two local split gates make a single channel be applicable to independently working switching devices, which are utilized as a logic device such as a NAND logic gate that is one of the universal gates. For conventional logic gates, two or more unit transistors are used, which requires additional metal electrodes, resulting in a larger footprint. We fabricated a logic device with a single channel of ReS2 and two graphene split gates. When the graphene split gate is used to locally modulate the channel, two regions, separately tuned by the split gates, act as independent transistors, which can be used as a gate-tunable NAND logic gate. The 2D-material-based NAND gate comprising a single transistor fabricated in this work provides a further step toward realization of “all-2D” circuitry for flexible and transparent electronic applications.

3D Sketch and optical image of our “all-2D” logic device realized in a single ReS2 channel. (Left and middle, respectively) This device shows reliable operation as a NAND gate logic. (Right)

If you want to see more, please find our paper recently published in Scientific Reports : All-2D ReS2 transistors with split gates for logic circuitry (

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